TrueConnect Welcomes You

In the first edition of Truechip's Annual Technical Conference being held at Bengaluru, India.
Trueconnect will focus on the innovative work and studies done by industry experts in the field of SoC Design, Verification and Integration.

Venue: Hotel Park Plaza, Bengaluru, India

Date: December 7, 2017 (Thursday)

Abstract & Paper Submission Schedule

Call for Abstract Submission opens

September 01, 2017

Call for Abstract Submission closes

October 16, 2017 (Date Extended to November 3, 2017)

Acceptance notification

November 10, 2017

Final Paper Submission due on

November 22, 2017

Conference and Presentation Day

December 07, 2017

  • Guidelines for Abstract
  • Guidelines for Paper
  • Guidelines for Presentation

▪ Proposed Paper title

▪ An introduction specifying the context and motivation of the submission.

▪ Description of the specific contributions of your work.

▪ Summary highlighting results.

▪ Mandatory to use the suggested template format .

▪ Must be approximately 2 pages and may include figures/diagrams/charts/tables

▪ References if required

▪ Paper length should be around 4+ pages, though there is no limitation on the length of the paper submitted

▪ The objective of the study and title/ An introduction that specifies the context and motivation of the submission.

▪ How the problem statement mentioned will provide solution or how the pain point will be eradicated by the solution you have proposed in your study.

▪ Mention the methodologies proposed/executed in conjunction with the study.

▪A summary that highlights results.

▪ The parameters of successful implementation of the study proposed/done.

▪ Must use the suggested template format

▪ References/Bibliography, if deemed necessary.

▪ Total presentation time is 25 minutes. The presentation should last for 20 minutes maximum with 5 minutes reserved for Q & A.

▪ The objective of the study and title/ An introduction that specifies the context and motivation of the submission.

▪ How the problem statement mentioned will provide solution or how the pain point will be eradicated by the solution you have proposed in your study.

▪ Mention the methodologies proposed/executed in conjunction with the study.

▪A summary that highlights results.

▪ The parameters of successful implementation of the study proposed/done.

▪ Must use the suggested template format (Attached with this email).

▪ Must be a minimum of 7-8 slides with maximum upto 15 slides (including figures/diagrams/charts/tables)

▪ References/Bibliography, if deemed necessary.

Criteria for Selection of Paper:

The paper will be evaluated by the panel of judges appointed by Truechip. The Top 7 Papers will be selected out of the total submissions who will present at the conference.

Significance of study

Technical Knowledge

Exclusivity of content

Methodologies used

Innovation used

Suggested Topics for Papers

Verification & Validation

▪ Advanced methodologies and testbenches

▪ Verification processes, regressions and resource management

▪ Debug and analysis of complex designs

▪ Multi-language design and verification

Safety-Critical Design & Verification

▪ Verification and DO-254 compliance

▪ Automotive ISO 26262 Design and Verification Challenges

▪ Medical or Industrial Verification Challenges

▪ Requirements-Driven Verification Methodologies

▪ IP protection and security

Machine Learning & Big Data

▪ Automating the Optimization of Verification Processes

▪ Coverage metrics and data analysis

▪ Performance modeling and/or analysis

Design & Verification reuse and Automation I

▪ Bridging verification and validation across multiple engines

▪ SoC and IP integration methods and tools

▪ Automated stimulus generation methods

▪ Configuration management of IP and abstraction levels

Design & Verification reuse and Automation II

▪ High-level synthesis from ESL languages

▪ Bridging virtual prototyping, simulation, emulation and/or FPGA prototyping

▪ Interoperability of models and/or tools

Low-Power Design & Verification

▪ Low-power design and verification

▪ Clock domain crossing verification

▪ Power modeling, estimation and management

In addition to the specific topic areas suggested above, submissions may incorporate:

  • ▪ Usage of Electronic Design Automation (EDA) tools such as simulation, emulation,
    formal verification, virtual prototyping and/or FPGA prototyping FPGA-based designs
  • ▪ Usage of specialized design and verification languages such as SystemVerilog, SystemC, and e
  • ▪ Assertions in SVA or PSL
  • ▪ The use of general purpose and scripting languages such as C, C++, Perl, Python, Tcl and others
  • ▪ Applications of the new Accellera Portable Stimulus Standard
  • ▪ Applications of design patterns or other innovative language techniques
  • ▪ The use of AMS languages
  • ▪ IoT Applications